obj-y    += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ 

config MTD_NAND_S3C2410   tristate "NAND Flash support for Samsung S3C SoCs"   depends on ARCH_S3C24XX || ARCH_S3C64XX   help    This enables the NAND flash controller on the S3C24xx and S3C64xx    SoCs     No board specific support is done by this driver, each board    must advertise a platform_device for the driver to attach.  config MTD_NAND_S3C2410_DEBUG   bool "Samsung S3C NAND driver debug"   depends on MTD_NAND_S3C2410   help    Enable debugging of the S3C NAND driver  config MTD_NAND_S3C2410_CLKSTOP   bool "Samsung S3C NAND IDLE clock stop"   depends on MTD_NAND_S3C2410   default n   help    Stop the clock to the NAND controller when there is no chip    selected to save power. This will mean there is a small delay    when the is NAND chip selected or released, but will save    approximately 5mA of power when there is nothing happening. 

obj-$(CONFIG_MTD_NAND_S3C2410)   += s3c2410.o 

static struct platform_driver s3c24xx_nand_driver = {   .probe   = s3c24xx_nand_probe,   .remove   = s3c24xx_nand_remove,   .suspend  = s3c24xx_nand_suspend,   .resume   = s3c24xx_nand_resume,   .id_table  = s3c24xx_driver_ids,   .driver   = {     .name  = "s3c24xx-nand",     .of_match_table = s3c24xx_nand_dt_ids,   }, };  module_platform_driver(s3c24xx_nand_driver); 

s3c2410_nand_init_chip(info, nmtd, sets); 

chip->write_buf  = s3c2410_nand_write_buf; chip->read_buf   = s3c2410_nand_read_buf; chip->select_chip = s3c2410_nand_select_chip; chip->chip_delay  = 50; nand_set_controller_data(chip, nmtd); chip->options    = set->options; chip->controller  = &info->controller;  switch (info->cpu_type) { case TYPE_S3C2410:   chip->IO_ADDR_W = regs + S3C2410_NFDATA;   info->sel_reg  = regs + S3C2410_NFCONF;   info->sel_bit  = S3C2410_NFCONF_nFCE;   chip->cmd_ctrl = s3c2410_nand_hwcontrol;   chip->dev_ready = s3c2410_nand_devready;   break;  case TYPE_S3C2440:   chip->IO_ADDR_W = regs + S3C2440_NFDATA;   info->sel_reg  = regs + S3C2440_NFCONT;   info->sel_bit  = S3C2440_NFCONT_nFCE;   chip->cmd_ctrl = s3c2440_nand_hwcontrol;   chip->dev_ready = s3c2440_nand_devready;   chip->read_buf = s3c2440_nand_read_buf;   chip->write_buf = s3c2440_nand_write_buf;   break;  case TYPE_S3C2412:   chip->IO_ADDR_W = regs + S3C2440_NFDATA;   info->sel_reg  = regs + S3C2440_NFCONT;   info->sel_bit  = S3C2412_NFCONT_nFCE0;   chip->cmd_ctrl = s3c2440_nand_hwcontrol;   chip->dev_ready = s3c2412_nand_devready;    if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)     dev_info(info->device, "System booted from NAND/n");    break; }