PC/AT 微機級聯式8259控制系統

The 8259 was introduced as part of Intel's MCS 85 family in 1976. The 8259A was included in the original PC introduced in 1981 and maintained by the PC/XT when introduced in 1983. A second 8259A was added with the introduction of the PC/AT. The 8259 has coexisted with the Intel APIC Architecture since its introduction in Symmetric Multi-PRocessor PCs. Modern PCs have begun to phase out the 8259A in favor of the Intel APIC Architecture. However, while not anymore a separate chip, the 8259A interface is still provided by the Southbridge chipset on modern x86 motherboards.

The main signal pins on an 8259 are as follows: eight interrupt input request lines named IRQ0 through IRQ7, an interrupt request output line named INTR, interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connections include CAS0 through CAS2 for cascading between 8259s.

Up to eight slave 8259s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.

There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). The IRR maintains a mask of the current interrupts that are pending acknowledgement, the ISR maintains a mask of the interrupts that are pending an EOI, and the IMR maintains a mask of interrupts that should not be sent an acknowledgement.

End Of Interrupt (EOI) Operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. Auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.

Edge and level interrupt trigger modes are supported by the 8259A. Fixed priority and rotating priority modes are supported.

The 8259 may be configured to work with an 8080/8085 or an 8086/8088. On the 8086/8088, the interrupt controller will provide an interrupt number on the data bus when an interrupt occurs. The interrupt cycle of the 8080/8085 will issue three bytes on the data bus (corresponding to a CALL instruction in the 8080/8085 instruction set).

The 8259A provides additional functionality compared to the 8259 (in particular buffered mode and level-triggered mode) and is upward compatible with it.

來自 <http://en.wikipedia.org/wiki/Intel_8259>

中斷信號通常分為兩類: 硬件中斷和軟件中斷, int 0x0 ~ int 0x1F 屬于軟件中斷(異常)[故障 + 陷阱], 在Linux 中, 將0x20 ~ 0x2F 對應于8259A中斷控制芯片發出的硬件請求信號 IRQ 0x0 ~ IRQ 0xF, 并把程序發出的系統調用中斷設置為 int 0x80

在Linux中, 內核首先使用一個啞中斷向量(中斷描述符)對中斷描述符表所有的256個描述符進行了默認設置, 這個啞中斷向量指向一個默認的"無中斷" 處理過程.

硬件異常(int 0x0 ~ int 0x01f)處理在文件 traps.c

系統調用中斷int 0x80 則在 sched.c 中進行了初始化.